Hi,
Been struggling to get consistant baud rate for USART2. I've tried the recent posts of setting the BRR value to 782. That value allowed some correct communication but was not 100%. I set the value to 778 and got good communication but only if I kept the CPU speed set to the middle position in the power config section.
My best solution still to this date is to have my own RCC configuration setup and then use the Circle OS default RCC configuration upon exit of the application. This allowed for good communication at any speed. I do not need to set the BRR value at all either using this method.
Here is my RCC config to get good communication:
void RCC_Config(void)
{
/* RCC system reset(for debug purpose) */
RCC_DeInit();
/* Enable HSE */
RCC_HSEConfig(RCC_HSE_ON);
/* Wait till HSE is ready */
HSEStartUpStatus = RCC_WaitForHSEStartUp();
if(HSEStartUpStatus == SUCCESS)
{
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
/* Flash 2 wait state */
FLASH_SetLatency(FLASH_Latency_2);
/* HCLK = SYSCLK */
RCC_HCLKConfig(RCC_SYSCLK_Div1);
/* PCLK2 = HCLK */
RCC_PCLK2Config(RCC_HCLK_Div1);
/* PCLK1 = HCLK/2 */
RCC_PCLK1Config(RCC_HCLK_Div2);
/* PLLCLK = 8MHz * 9 = 72 MHz */
// RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
/* Enable PLL */
RCC_PLLCmd(ENABLE);
/* Wait till PLL is ready */
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
{
}
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
/* Wait till PLL is used as system clock source */
while(RCC_GetSYSCLKSource() != 0x08)
{
}
}
}
Here is the RCC configuration I used upon exit of the application:
void RCC_Configuration( void )
{
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
/* RCC system reset(for debug purpose) */
RCC_DeInit();
/* Enable HSE */
RCC_HSEConfig( RCC_HSE_ON );
/* Wait till HSE is ready */
while( RCC_GetFlagStatus( RCC_FLAG_HSERDY ) == RESET )
{;}
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
/* Flash 2 wait state */
FLASH_SetLatency(FLASH_Latency_2);
/* HCLK = SYSCLK */
RCC_HCLKConfig( RCC_SYSCLK_Div1 );
/* PCLK2 = HCLK */
RCC_PCLK2Config( RCC_HCLK_Div1 );
/* PCLK1 = HCLK/2 */
RCC_PCLK1Config( RCC_HCLK_Div2 );
/* ADCCLK = PCLK2/6 */
RCC_ADCCLKConfig( RCC_PCLK2_Div6 );
/* Flash 2 wait state */
*(vu32 *)0x40022000 = 0x02;
/* Set CPU clock */
//UTIL_SetPll( UTIL_ReadBackupRegister( BKP_PLL ) ); //YRT 20081025 : data compaction in bit format
UTIL_SetPll( UTIL_ReadBackupRegister( BKP_SYS2 ) & 0x0007 );
/* Enable GPIOB & GPIOB clock */
RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB, ENABLE );
/* Enable GPIOB clock */
//RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA, ENABLE );
/* Enable TIM2 */
RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM2, ENABLE );
}
Not sure why it is but it works for my Primer2 devices.
