CircleOS: Util_spe2.c Source File

00001 /****************** COPYRIGHT (C) 2007-2010 RAISONANCE S.A.S. *****************/
00010 /******************************************************************************/
00011 
00012 /* Includes ------------------------------------------------------------------*/
00013 #include "circle.h"
00014 
00016 
00017 /* Private defines -----------------------------------------------------------*/
00018 #define  VDD_VOLTAGE_MV  3150 /* Voltage (mV) of the STM32*/
00019 
00020 /* Private typedef -----------------------------------------------------------*/
00021 
00022 /* Private variables ---------------------------------------------------------*/
00023 RCC_ClocksTypeDef    RCC_ClockFreq;
00024 s16                  VBat = -1;
00025 
00026 /* Private function prototypes -----------------------------------------------*/
00027 
00028 /* Private functions ---------------------------------------------------------*/
00029 
00030 /* External variables ---------------------------------------------------------*/
00031 
00032 /* Public functions ----------------------------------------------------------*/
00033 
00034 /*******************************************************************************
00035 *
00036 *                                UTIL_isBackupRegisterConfigured
00037 *
00038 *******************************************************************************/
00046 /******************************************************************************/
00047 bool UTIL_isBackupRegisterConfigured( void )
00048 {
00049     int i;
00050 
00051     for ( i = 1 ; i <= 11 ; i++ )
00052     {
00053         if ( UTIL_ReadBackupRegister( i ) != 0 )
00054             return TRUE;
00055     }
00056 
00057     return FALSE;
00058 }
00059 
00060 
00061 /*******************************************************************************
00062 *
00063 *                                SetBitTimingAnalysis
00064 *
00065 *******************************************************************************/
00075 /********************************************************************************/
00076 void SetBitTimingAnalysis( u8 set )
00077 {
00078     if ( set )
00079     {
00080         GPIO_WriteBit( GPIOA, GPIO_Pin_3, Bit_SET );
00081     }
00082     else
00083     {
00084         GPIO_WriteBit( GPIOA, GPIO_Pin_3, Bit_RESET );
00085     }
00086 }
00087 
00089 
00090 /*******************************************************************************
00091 *
00092 *                    UTIL_GetBat
00093 *
00094 *******************************************************************************/
00102 /******************************************************************************/
00103 u16 UTIL_GetBat( void )
00104 {
00105     u16 vbat;
00106     vs32 i;
00107 
00108     // Measures VBAT and calculates the mean value
00109     vbat = 0;
00110     for ( i = 0; i < ADC_NB_SAMPLES; i++ )
00111     {
00112         vbat += ADC_ConvertedValue[0 + i * ADC_NB_CHANNELS];
00113     }
00114     vbat = vbat / ADC_NB_SAMPLES;
00115 
00116     vbat = vbat & 0xFFF;
00117     vbat = ( vbat * VDD_VOLTAGE_MV ) / 0x1000;
00118 
00119     vbat *= 2; //Divider bridge  Vbat <-> 1M -<--|-->- 1M <-> Gnd,
00120 
00121     if ( VBat == -1 )
00122     {
00123         VBat = vbat;
00124     }
00125     else
00126     {
00127         VBat = ( VBat >> 1 ) + ( vbat >> 1 );
00128     }
00129     return VBat;
00130 }
00131 
00132 /*******************************************************************************
00133 *
00134 *                    UTIL_GetTemp
00135 *
00136 *******************************************************************************/
00144 /******************************************************************************/
00145 u16 UTIL_GetTemp( void )
00146 {
00147     u16 temp;
00148     vs32 i;
00149 
00150     // Calculate the mean value
00151     temp = 0;
00152     for ( i = 0; i < ADC_NB_SAMPLES; i++ )
00153     {
00154         temp += ADC_ConvertedValue[1 + i*ADC_NB_CHANNELS];
00155     }
00156     temp = temp / ADC_NB_SAMPLES;
00157 
00158     temp = temp & 0xFFF;
00159     temp = ( temp * VDD_VOLTAGE_MV ) / 0x1000;  //finds mV
00160     temp = ((( 1430 - temp ) * 100000 ) / 4300 ) + 25000; //gives approx temp x 1000 degrees C
00161 
00162     //Fahrenheit = 32 + 9 / 5 * Celsius
00163     if ( fTemperatureInFahrenheit )
00164     {
00165         temp = 32000 + ( 9 * temp ) / 5 ;
00166     }
00167 
00168     return temp / 100;
00169 }
00170 
00171 
00172 /*******************************************************************************
00173 *
00174 *                                UTIL_SetPll
00175 *
00176 *******************************************************************************/
00187 /******************************************************************************/
00188 void UTIL_SetPll( enum eSpeed speed )
00189 {
00190     /* Select internal clok as system clock source */
00191     RCC_SYSCLKConfig( RCC_SYSCLKSource_HSI );
00192 
00193     /* Disable PLL */
00194     RCC_PLLCmd( DISABLE );
00195 #ifdef STM32F10X_CL
00196     RCC_PLL2Cmd( DISABLE );
00197 #endif
00198 
00199     if (( speed < SPEED_VERY_LOW ) || ( speed > SPEED_VERY_HIGH ) )
00200     {
00201         speed = SPEED_MEDIUM;
00202     }
00203 
00204     CurrentSpeed = speed;
00205 
00206     switch ( speed )
00207     {
00208         // 18 MHz
00209     case SPEED_VERY_LOW  :
00210 #ifdef STM32F10X_CL
00211         // Source PLLCLK = PLL2
00212         RCC->CFGR2 &= ( uint32_t )~( RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL  |
00213                                      RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC );
00214         RCC->CFGR2 |= ( uint32_t )( RCC_CFGR2_PREDIV2_DIV4 | RCC_CFGR2_PLL2MUL12 |
00215                                     RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_I2S2SRC );
00216         /* PLL configuration: PLLCLK = (PLL2CLK / 16) * 6.5 = 17.97 MHz */
00217         RCC->CFGR &= ( uint32_t )~( RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL );
00218         RCC->CFGR |= ( uint32_t )( RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL6_5 );
00219 #else
00220         /* PLLCLK = 6MHz * 3 = 18 MHz */
00221         RCC_PLLConfig( RCC_PLLSource_HSE_Div2, RCC_PLLMul_3 );
00222 #endif
00223         break;
00224 
00225         // 24MHz
00226     case SPEED_LOW       :
00227 #ifdef STM32F10X_CL
00228         // Source PLLCLK = PLL2
00229         RCC->CFGR2 &= ( uint32_t )~( RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00230                                      RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC );
00231         RCC->CFGR2 |= ( uint32_t )( RCC_CFGR2_PREDIV2_DIV4 | RCC_CFGR2_PLL2MUL12 |
00232                                     RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_I2S2SRC );
00233         /* PLL configuration: PLLCLK = (PLL2CLK / 9) * 5 = 24.58 MHz */
00234         RCC->CFGR &= ( uint32_t )~( RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL );
00235         RCC->CFGR |= ( uint32_t )( RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL5 );
00236 #else
00237         /* PLLCLK = 12MHz * 2 = 24 MHz */
00238         RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_2 );
00239 #endif
00240         break;
00241 
00242         // 36MHz
00243     default              :
00244         CurrentSpeed = SPEED_MEDIUM;
00245     case SPEED_MEDIUM    :
00246 #ifdef STM32F10X_CL
00247         // Source PLLCLK = PLL2
00248         RCC->CFGR2 &= ( uint32_t )~( RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00249                                      RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC );
00250         RCC->CFGR2 |= ( uint32_t )( RCC_CFGR2_PREDIV2_DIV4 | RCC_CFGR2_PLL2MUL12 |
00251                                     RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_I2S2SRC );
00252         /* PLL configuration: PLLCLK = (PLL2CLK / 8) * 6.5 = 35.94 MHz */
00253         RCC->CFGR &= ( uint32_t )~( RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL );
00254         RCC->CFGR |= ( uint32_t )( RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL6_5 );
00255 #else
00256         /* PLLCLK = 12MHz * 3 = 36 MHz */
00257         RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_3 );
00258 #endif
00259         break;
00260 
00261         // 48MHz
00262     case SPEED_HIGH      :
00263 #ifdef STM32F10X_CL
00264         // Source PLLCLK = PLL2
00265         RCC->CFGR2 &= ( uint32_t )~( RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00266                                      RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC );
00267         RCC->CFGR2 |= ( uint32_t )( RCC_CFGR2_PREDIV2_DIV4 | RCC_CFGR2_PLL2MUL12 |
00268                                     RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_I2S2SRC );
00269         /* PLL configuration: PLLCLK = (PLL2CLK / 8) * 9 = 49.77 MHz */
00270         RCC->CFGR &= ( uint32_t )~( RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL );
00271         RCC->CFGR |= ( uint32_t )( RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9 );
00272 #else
00273         /* PLLCLK = 12MHz * 4 = 48 MHz */
00274         RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_4 );
00275 #endif
00276         break;
00277 
00278         // 72MHz
00279     case SPEED_VERY_HIGH :
00280 #ifdef STM32F10X_CL
00281         // Source PLLCLK = PLL2
00282         RCC->CFGR2 &= ( uint32_t )~( RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
00283                                      RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC );
00284         RCC->CFGR2 |= ( uint32_t )( RCC_CFGR2_PREDIV2_DIV4 | RCC_CFGR2_PLL2MUL12 |
00285                                     RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_I2S2SRC );
00286         /* PLL configuration: PLLCLK = (PLL2CLK / 4) * 6.5 = 71.88 MHz */
00287         RCC->CFGR &= ( uint32_t )~( RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL );
00288         RCC->CFGR |= ( uint32_t )( RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL6_5 );
00289 #else
00290         /* PLLCLK = 12MHz * 6 = 72 MHz */
00291         RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_6 );
00292 #endif
00293         break;
00294     }
00295 
00296 #ifdef STM32F10X_CL
00297     /* Enable PLL2 */
00298     RCC_PLL2Cmd( ENABLE );
00299 
00300     /* Wait till PLL2 is ready */
00301     while (( RCC->CR & RCC_CR_PLL2RDY ) == 0 )
00302     {
00303     }
00304 #endif
00305 
00306     /* Enable PLL */
00307     RCC_PLLCmd( ENABLE );
00308 
00309     /* Wait till PLL is ready */
00310     while (( RCC->CR & RCC_CR_PLLRDY ) == 0 )
00311     {
00312     }
00313 
00314     /* Select PLL as system clock source */
00315     RCC_SYSCLKConfig( RCC_SYSCLKSource_PLLCLK );
00316 
00317     /* Wait till PLL is used as system clock source */
00318     while (( RCC->CFGR & ( uint32_t )RCC_CFGR_SWS ) != ( uint32_t )0x08 )
00319     {
00320     }
00321 
00322     /* This function fills a RCC_ClocksTypeDef structure with the current frequencies
00323     of different on chip clocks (for debug purpose) */
00324     RCC_GetClocksFreq( &RCC_ClockFreq );
00325 
00326 #if AUDIO_AVAIL
00327 #ifndef STM32F10X_CL
00328     extern const u16 I2S_PrescalerVal[];
00329     // Set the prescaler values for the I2S (audio codec) according to the PLL
00330     *( u16* )AUDIO_I2SPR = I2S_PrescalerVal[speed-1];
00331 #endif
00332 #endif
00333 }
00334 
00335 
00336 /*******************************************************************************
00337 *
00338 *                                UTIL_ReadBackupRegister
00339 *
00340 *******************************************************************************/
00350 /******************************************************************************/
00351 backup_t UTIL_ReadBackupRegister( index_t BKP_DR )
00352 {
00353     if ( BKP_DR < 11 )
00354     {
00355         return ( *( vu16* )( BKP_BASE + 4 * BKP_DR ) );
00356     }
00357     else if ( BKP_DR < 43 )
00358     {
00359         return ( *( vu16* )( BKP_BASE + 4 * ( BKP_DR + 5 ) ) );
00360     }
00361     else return 0;
00362 }
00363 
00364 /*******************************************************************************
00365 *
00366 *                                UTIL_WriteBackupRegister
00367 *
00368 *******************************************************************************/
00377 /********************************************************************************/
00378 void UTIL_WriteBackupRegister( index_t BKP_DR, backup_t Data )
00379 {
00380     if ( BKP_DR < 11 )
00381     {
00382         *( vu16* )( BKP_BASE + 4 * BKP_DR ) = Data;
00383     }
00384     else if ( BKP_DR < 43 )
00385     {
00386         *( vu16* )( BKP_BASE + 4 *( BKP_DR + 5 ) ) = Data;
00387     }
00388 }
00389 
00390 /*******************************************************************************
00391 *
00392 *                                UTIL_GetPrimerType
00393 *
00394 *******************************************************************************/
00404 /********************************************************************************/
00405 u16 UTIL_GetPrimerType( void )
00406 {
00407     return PRIMER_TYPE;
00408 }