Thank you for a helpful answer!
> As TRGO is generated when the bit TG is set in event register (TIMx_EGR),
ok
>CCx events are generated when bit CCxG are set in the same register,
This is not generally true. I can toggle the TIM1_EGR CC1G bit in Ride 7. This does not trigger an ADC conversion. Maybe it does when other settings are correctly configured.
> after configuring the event with the capture/compare mode register x (TIMx_CCMRx),
> and the capture/compare register x (TIMx_CCRx).
Ok, but this is not specified in RM0008.
> In your case, configure an output compare channel (TIM_CC1, CC2 or CC3).
> Take a look at this chaper of the Reference Manual 008 :
> "13.3.5 Capture/compare channels".
I have read the timer section carefully. Repeatedly. Section 13.3.5 says nothing at all about CC events. The output compare mode is in section 13.3.9, which states that when a match occurs:
- An output pin is assigned a value (presumably not needed for an internal signal path)
- Sets an interrupt status register flag
- Generates an interrupt, if requested
- Sends a DMA request
No mention of CC trigger events for other peripherals.
> Did you look after examples in the ST libraries examples ?
Thank you! This was a useful suggestion, as I found a relevant code section in one of the
ADC examples. Apparently, it is necessary to configure the Timer in PWM mode,
the OIS1 bit in CR2 must be set to 1 and the OIS1N bit must be zero.
I can now trigger ADC1 with TIM1_CC1 events.
None of this information is in the data sheet or the programming guide.
For evaluating Primer2, documentation by example is ok. For actual application,
I can not use processor features that are not explicitly documented by the manufacturer,
apparently for product liability reasons.
But thank you for the answer. I really do appreciate the feedback.
